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https://link.springer.com/content/pdf/10.1007/s00034-021-01855-x.pdf
Circuits, Systems, and Signal Processing (2022) 41:1683–1703
Published online: 2nd December 2021
Article title: "High-Radix Formats for Enhancing Floating-Point FPGA Implementations"
Authors: Julio Villalba, Javier Hormigo
Extracts:
Circuits, Systems, and Signal Processing (2022) 41:1683–1703
Published online: 2nd December 2021
Article title: "High-Radix Formats for Enhancing Floating-Point FPGA Implementations"
Authors: Julio Villalba, Javier Hormigo
Extracts:
- "For applications with similar numbers of additions and multiplications, the
high-radix version may be up to 26% faster" - "We propose using a radix 2^r (with r being an integer and r > 1) for the base of the
representation of a FP number instead of radix 2." - "there is a striking speedup for radix 16 and 64"
- "In conclusion, for balanced codes, two good trade-off solutions are radix 16
and 64 (radix 16 is slightly faster than radix 64 (+1.7%) with a little more area (+9%)).
However, it depends on the specific constraints, and each case needs a careful study,
and this evaluation may help to perform it." - "there is a net gain for our designs of radix 16 (+26%), 64 (+23%), and 256 (+16%). For radix 4096 and above,
these implementations are ineffective." - "Summarizing, among the studies designs, the fastest architecture for algorithms in
which addition is dominant is radix 16 and the best area is obtained for radix 256. For
algorithms in which multiplication is dominant, regular radix 2 is the best option, but
for balanced codes (predominant in many algorithms), the best speed is obtained with
radix 16, the best area with radix 256, and a good trade-off solution is obtained with
radix 64."
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